DTR: a defect-tolerant routing algorithm
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Post-route optimization for improved yield using a rubber-band wiring model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The road to better reliability and yield embedded DFM tools
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Stay away from minimum design-rule values
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Synthesis for Manufacturability: A Sanity Check
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An up-stream design auto-fix flow for manufacturability enhancement
Proceedings of the 43rd annual Design Automation Conference
Robust wiring networks for DfY considering timing constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
Proceedings of the 2009 International Conference on Computer-Aided Design
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Automated design tools produce layouts complying with all design rules (DRs). However, most wires are designed with minimum width, making them susceptible to random defect induced interruptions (opens). Spaces between wires are also often designed at minimum size, causing yield loss from random defect induced connections (shorts). SFF ("Spread - Fatten - Fill") is a methodology to improve layout - specifically for routing metal layers - in terms of yield loss related to opens and shorts. Additionally, a novel fill concept improves metal density uniformity. In this paper, we will explain issues that were observed and addressed in the implementation on a real layout, and present results achieved in the first experiment on silicon.