Design for manufacturability and yield
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Design for testability view on placement and routing
EURO-DAC '92 Proceedings of the conference on European design automation
Cost of silicon viewed from VLSI design perspective
DAC '94 Proceedings of the 31st annual Design Automation Conference
Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Inductive Contamination Analysis (ICA) with SRAM Application
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Detection of an antenna effect in VLSI designs
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Extraction of critical areas for opens in large VLSI circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Testability-oriented channel routing
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications
CAD at the design-manufacturing interface
DAC '97 Proceedings of the 34th annual Design Automation Conference
Cost based tradeoff analysis of standard cell designs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Modeling the Economics of Testing: A DFT Perspective
IEEE Design & Test
Understanding metrics in logic synthesis for routability enhancement
Proceedings of the 2003 international workshop on System-level interconnect prediction
A Quantitative Approach to Nonlinear Process Design Rule Scaling
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Current Signatures: Application
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Current Signatures: Application
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Synthesis for Manufacturability: A Sanity Check
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Issues in the development of a practical NoC: the Proteo concept
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
A methodology for fast and accurate yield factor estimation during global routing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Implementation of a contradiction-based approach to DFM
International Journal of Computer Integrated Manufacturing
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Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) trade-offs. Yield and cost models needed to analyze these trade-offs are explained as well.