Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance - manufacturability tradeoffs in IC design
Proceedings of the conference on Design, automation and test in Europe
Manufacturability and Testability Oriented Synthesis
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Maximizing Wafer Productivity Through Layout Optimization
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
DFM Metrics for Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Timing-aware cell layout de-compaction for yield optimization by critical area minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synthesis stage and has been shown capable of reducing manufacturing cost up to 10%. As in other cases, raising the abstraction layer where optimization is applied is expected to yield substantial gains. This paper focuses on a new approach to design for manufacturability: logic synthesis for manufacturability. This methodology consists of replacing the traditional area-driven technology mapping with a new manufacturability-driven one. We leverage existing logic synthesis tools to test our method. The results obtained by using STMicroelectronics 0.13µm library confirm that this approach is a promising solution for designing circuits with lower manufacturing cost, while retaining performance. Finally, we show that our synthesis for manufacturability can achieve even larger cost reduction when yield-optimized cells are added to the library, thus enabling a wider area-yield tradeoff exploration.