Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Layout compaction for yield optimization via critical area minimization
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Synthesis for Manufacturability: A Sanity Check
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Automated testability enhancements for logic brick libraries
Proceedings of the conference on Design, automation and test in Europe
Lithography-aware layout compaction
Proceedings of the great lakes symposium on VLSI
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This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard cells and the proposed method automatically creates yield-enhanced cell layouts by de-compacting the original cell layout. However, the careless modification of the original layout may degrade its performances severely. Therefore, the proposed method de-compacts the original layout under given timing constraints using a Linear Programming (LP). We develop a new accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints in the LP. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the trade off curve of cell delay versus critical area and is used to create the yield-enhanced cell library which is essential to realize yield-aware VLSI design flows.