Generic ILP versus specialized 0-1 ILP: an update
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Systematic DFT Procedure for Library Cells
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
EDA for IC System Design, Verification, and Testing (Electronic Design Automation for Integrated Circuits Handbook)
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
| Hi-index | 0.00 |
Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT formulation of the brick routing has been developed to minimize wire length and the number of vias while maintaining several design-for-manufacturability constraints. In this work, testability enhancements are imposed into a logic brick to reduce the likelihood of (i) feedback bridges to improve test and (ii) equivalent faults to improve diagnosis. This is accomplished by adding constraints to the SAT formulation of the logic brick routing that restricts certain wires from being routed in close proximity, thus making bridges between them unlikely. Application to several brick designs resulted in critical-area reductions for targeted bridges with little degradation in terms of additional wire length and via count.