Whirlpool PLAs: a regular logic structure and their synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Exploring Logic Block Granularity for Regular Fabrics
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design methodology and tools for NEC electronics' structured ASIC ISSP
Proceedings of the 2004 international symposium on Physical design
Design considerations for regular fabrics
Proceedings of the 2004 international symposium on Physical design
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
On designing via-configurable cell blocks for regular fabrics
Proceedings of the 41st annual Design Automation Conference
Routing architecture exploration for regular fabrics
Proceedings of the 41st annual Design Automation Conference
Pattern sensitive placement for manufacturability
Proceedings of the 2007 international symposium on Physical design
Variability and yield improvement: rules, models, and characterization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
OPC-free and minimally irregular IC design style
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Automated testability enhancements for logic brick libraries
Proceedings of the conference on Design, automation and test in Europe
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
Manufacturability-Aware Design of Standard Cells
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Total sensitivity based dfm optimization of standard library cells
Proceedings of the 19th international symposium on Physical design
Performance study of VeSFET-based, high-density regular circuits
Proceedings of the 19th international symposium on Physical design
Layout generator for transistor-level high-density regular circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
On process-aware 1-D standard cell design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mask cost reduction with circuit performance consideration for self-aligned double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Transistor sizing in lithography-aware regular fabrics
Proceedings of the 24th symposium on Integrated circuits and systems design
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
The evolution of standard cell libraries for future technology nodes
Genetic Programming and Evolvable Machines
Impact of lithography retargeting process on low level interconnect in 20nm technology
Proceedings of the International Workshop on System Level Interconnect Prediction
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
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Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns [6,7] can provide significant advantages in terms of manufacturability and design cost [2]. Various forms of gate and logic arrays have been recently proposed that can offer such pattern regularity to reduce design risk and costs [2,4,9,11,12]. In this paper, we propose a full-mask-set design methodology which provides the same physical design coherence as a configurable array, but with area and other design benefits comparable to standard cell ASICs. This methodology is based on a set of simple logic primitives that are mapped to a set of logic bricks that are defined by a restrictive set of RET(Resolution Enhancement Technique)-friendly geometry patterns. We propose a design methodology to explore trade-offs between the number of bricks and associated level of configurability versus the required silicon area. Results are shown to compare a design implemented with a small number of regular bricks to an implementation based on a full standard cell library in a 90nm CMOS technology.