An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
Flexible ASIC: shared masking for multiple media processors
Proceedings of the 42nd annual Design Automation Conference
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A methodology for FPGA to structured-ASIC synthesis and verification
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A low-SER efficient core processor architecture for future technologies
Proceedings of the conference on Design, automation and test in Europe
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Application-Specific FPGA using heterogeneous logic blocks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Microprocessors & Microsystems
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and design flow for a highly efficient structured ASIC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
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Structured ASICs are an emerging new class of ASICs that attempt to bridge the widening gap in per-unit manufacturing costs, non recurring engineering (NRE) costs, power consumption, and performance between zero-mask programmable devices such as FPGAs and devices such as cell based ASICs, which require new custom designed masks for every ASIC. They offer an intermediate trade-off point between the two extremes of the very high per unit cost, but zero non-recurring cost of FPGAs, and the very low per unit cost, but very high non-recurring cost of cell based ASICs. They also offer a similar, intermediate trade-off point between the two extremes for performance and power consumption. A common theme across all structured ASICs is the use of a circuit fabric that has a regular, repeating pattern of elementary building blocks that can be programmed using one or more masks to implement an ASIC device. In this paper, we describe the considerations involved in designing the regular circuit fabrics underlying structured ASIC offerings.