PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Rent's rule based switching requirements
Proceedings of the 2001 international workshop on System-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Design methodology and tools for NEC electronics' structured ASIC ISSP
Proceedings of the 2004 international symposium on Physical design
Design considerations for regular fabrics
Proceedings of the 2004 international symposium on Physical design
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Automatic Design of Area-Efficient Configurable ASIC Cores
IEEE Transactions on Computers
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Comparison between heterogeneous mesh-based and tree-based application specific FPGA
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A heterogeneous Application Specific FPGA (ASIF) is a modified form of heterogeneous FPGA which is designed to explore the solution space between FPGAs and ASICs. Compared to an equivalent FPGA architecture, it has reduced flexibility but improved density. On the other hand, compared to an ASIC, it has reconfigurability but increased area. This work presents a new heterogeneous tree-based ASIF. Four ASIF generation techniques are explored for it using 17 benchmarks. Experimental results show that, on average, the best ASIF generation technique gives 70% area gain when compared to an equivalent FPGA architecture. Further experiments are performed to determine the effect of Lookup-Table (LUT) and arity size on heterogeneous tree-based ASIF. Later, area comparison between tree-based ASIF and equivalent mesh-based ASIF shows that the former gives either equal or better results than the latter. Finally quality comparison of two ASIFs shows that, on average, tree-based ASIF produces 18% better area results than mesh-based ASIF.