An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
Fishbone: a block-level placement and routing scheme
Proceedings of the 2003 international symposium on Physical design
IEEE Design & Test
Fast, cheap and under control: the next implementation fabric
Proceedings of the 40th annual Design Automation Conference
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
Flexible ASIC: shared masking for multiple media processors
Proceedings of the 42nd annual Design Automation Conference
Analysis and modeling of power grid transmission lines
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A methodology for FPGA to structured-ASIC synthesis and verification
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Architectural implications of brick and mortar silicon manufacturing
Proceedings of the 34th annual international symposium on Computer architecture
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
RegPlace: a high quality open-source placement framework for structured ASICs
Proceedings of the 46th Annual Design Automation Conference
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
Register placement for high-performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Microprocessors & Microsystems
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and design flow for a highly efficient structured ASIC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of via-configurable routing fabrics for structured ASICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
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In this paper, we describe a design methodology and tools for NEC Electronics' structured ASIC, Instant Silicon Solution Platform (ISSP), which is being developed to fill the gap between FPGAs and standard cell-based ASICs. The ISSP has a unique regular-fabric architecture designed to achieve both a short time to production and high-performance LSI design. We have developed a special design methodology and tools to fully exploit the capability of this new device. Experimental results for industrial data show that our approach has advantages for ISSP design.