MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
Fishbone: a block-level placement and routing scheme
Proceedings of the 2003 international symposium on Physical design
A hybrid ASIC and FPGA architecture
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Designing mega-ASICs in nanogate technologies
Proceedings of the 40th annual Design Automation Conference
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Design methodology and tools for NEC electronics' structured ASIC ISSP
Proceedings of the 2004 international symposium on Physical design
Design considerations for regular fabrics
Proceedings of the 2004 international symposium on Physical design
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
On designing via-configurable cell blocks for regular fabrics
Proceedings of the 41st annual Design Automation Conference
Routing architecture exploration for regular fabrics
Proceedings of the 41st annual Design Automation Conference
What is the next implementation fabric?
IEEE Design & Test
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ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micron manufacturability) trends favor FPGA as an implementation platform. In order to combine the advantages of both platforms and alleviate their disadvantages, recently a number of approaches, such as structured ASIC/regular fabrics, have been proposed. Our goal is to introduce an approach that has the same objective, but is orthogonal to those already proposed. The idea is to implement several ASIC designs in such a way that they share the datapath, memory structure, and several bottom layers of interconnect, while each design has only a few unique metal layers. We identified and addressed two main problems in our quest to develop a CAD flow for realization of such designs. They are: (i) the creation of the datapath, and (ii) the identification of common and unique interconnects for each design. Both problems are solved optimally using ILP formulations. We assembled a design flow platform using two new programs and the Trimaran and Shade tools. We quantitatively analyzed the advantages and disadvantages of the approach using the Mediabench benchmark suite.