Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Design Challenges of Technology Scaling
IEEE Micro
A hybrid ASIC and FPGA architecture
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Issues and strategies for the physical design of system-on-a-chip ASICs
IBM Journal of Research and Development
Early analysis tools for system-on-a-chip design
IBM Journal of Research and Development
The IBM ASIC/SoC methodology--A recipe for first-time success
IBM Journal of Research and Development
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Maintaining the benefits of CMOS scaling when scaling bogs down
IBM Journal of Research and Development
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early probabilistic noise estimation for capacitively coupled interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Flexible ASIC: shared masking for multiple media processors
Proceedings of the 42nd annual Design Automation Conference
| Hi-index | 0.00 |
This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities possible in the latest silicon technologies. Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas are presented. Lastly, this paper discusses the integration of multiple functional components (previously organized as systems of multiple chips from multiple design sources and technologies) into a single chip product.