Statistical timing for parametric yield prediction of digital integrated circuits

Authors:
J. A. G. Jess;K. Kalafala;S. R. Naidu;R. H. J. M. Otten;C. Visweswariah
Affiliations:
Eindhoven University of Technology, Eindhoven, The Netherlands;IBM Microelectronics Division, East Fishkill, NY;Eindhoven University of Technology, Eindhoven, The Netherlands;Eindhoven University of Technology, Eindhoven, The Netherlands;IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Venue:
Proceedings of the 40th annual Design Automation Conference
Year:
2003

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Abstract

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by EinsTimer's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.