Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power efficiency for variation-tolerant multicore processors
Proceedings of the 2006 international symposium on Low power electronics and design
Power management of variation aware chip multiprocessors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Variation-tolerant dynamic power management at the system-level
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware system-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Recovery-based design for variation-tolerant SoCs
Proceedings of the 49th Annual Design Automation Conference
Variation-aware voltage level selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware leakage power model extraction for system-level hierarchical power analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Leak-Gauge: A late-mode variability-aware leakage power estimation framework
Microprocessors & Microsystems
Static statistical MPSoC power optimization by variation-aware task and communication scheduling
Microprocessors & Microsystems
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Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various design techniques to address process variations at the mask, circuit, and logic levels. However, as the magnitude of process variations increases, their effects will need to be addressed earlier in the design cycle.In this paper, we propose techniques for accurately and efficiently incorporating the effects of process variations into system-level power estimation tools. To motivate our work, we first study the impact of process variations on the power consumption of an example System-on-Chip (SoC). We consider simple extensions of current approaches to system-level power estimation (spreadsheet-based and simulation-based power estimation), and demonstrate their limitations in performing variation-aware power estimation. We propose a system-level power estimation methodology that can accurately and efficiently analyze the impact of process variations on SoC power. The proposed methodology combines efficient trace-based analysis, power-state based leakage modeling, and Monte Carlo sampling. The key benefit of the proposed methodology is that it captures the necessary inter-dependencies while avoiding iterative system-level simulation. Our implementation of the proposed techniques within an in-house system-level power estimation framework indicates 2-5 orders of magnitude efficiency gains, with negligible loss in accuracy, compared to direct Monte Carlo techniques that require iterative system simulation.