PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Accelerating system-on-chip power analysis using hybrid power estimation
Proceedings of the 44th annual Design Automation Conference
A multi-model power estimation engine for accuracy optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
Variation-tolerant dynamic power management at the system-level
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware system-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-model engine for high-level power estimation accuracy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs
Proceedings of the 48th Design Automation Conference
A very fast and quasi-accurate power-state-based system-level power modeling methodology
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
Variation-aware voltage level selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
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Paper analysis early in the design cycle is critical for the design of low-power systems. With the move to system-level specifications and design methodologies, there has been significant research interest in system-level power estimation. However, as demonstrated in this paper, the addition of power estimation capabilities to system-level simulation tools can significantly degrade simulation efficiency (upto 8.5X), limiting the use of power estimation during long simulation runs, and the ability to perform extensive design space exploration. Some power modeling techniques for system components provide "local" tradeoffs between power estimation accuracy and computational cost. This work addresses a complementary problem 驴 the optimized integration and usage of heterogeneous component power models within a system-level simulation framework. We view system-level power estimation as a global deployment of computational effort (the effort required to perform power estimation) over space (the different components) and time (the duration of the simulation). We illustrate the advantages of optimizing the allocation of power estimation effort based on run-time variations of component-level, as well as system-level power consumption characteristics. To achieve this, we have developed a novel power estimation framework, based on a network of power monitors. Power monitors observe component- and system-level execution and power statistics at run time, based on which they (i) select between multiple alternative power models for each component, and/or (ii) configure the component power models, to best negotiate the trade-off between efficiency and accuracy. In effect, the power monitor network performs a co-ordinated, adaptive, spatio-temporal allocation of computational effort for power estimation. Experiments conducted on a commercial system-level simulation framework and System-on-Chip platform demonstrate that the proposed techniques yield large reductions in power estimation overhead (nearly and order of magnitude), while minimally impacting power estimation accuracy.