Early power exploration—a World Wide Web application
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Policy optimization for dynamic power management
DAC '98 Proceedings of the 35th annual Design Automation Conference
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
State-based power analysis for systems-on-chip
Proceedings of the 40th annual Design Automation Conference
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Actor-oriented models for codesign: balancing re-use and performance
Formal methods and models for system design
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
On robust task-accurate performance estimation
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
In this paper, we propose a novel system-level power modeling methodology that allows for very fast joint power-performance evaluation at specification phase. This methodology adopts approximately-timed task-accurate performance models and augments them with power-state-based power models to enable efficient simulation. A flexible method is also proposed to model complex dynamic power management policies so that their effects can be evaluated. We validate the accuracy of our methodology by comparing simulation results with measurements on a real mobile phone platform. Experimental results show that the simulated power profile matches very well with the measurements and it only takes about 100 ms to simulate a 20 ms GSM paging burst use case.