Early power exploration—a World Wide Web application
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
PowerPC 603, A Microprocessor for Portable Computers
IEEE Design & Test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
ESL power analysis of embedded processors for temperature and reliability estimations
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power aware SID-based simulator for embedded multicore DSP subsystems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Co-optimization of performance and power in a superscalar processor design
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
A very fast and quasi-accurate power-state-based system-level power modeling methodology
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
System-level modeling of energy in TLM for early validation of power and thermal management
Proceedings of the Conference on Design, Automation and Test in Europe
Variation-aware leakage power model extraction for system-level hierarchical power analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.