Proceedings of the 6th international workshop on Hardware/software codesign
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
State-based power analysis for systems-on-chip
Proceedings of the 40th annual Design Automation Conference
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A provably good approximation algorithm for power optimization using multiple supply voltages
Proceedings of the 44th annual Design Automation Conference
Logic and Layout Aware Voltage Island Generation for Low Power Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Voltage Island Generation under Performance Requirement for SoC Designs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimality and scalability study of existing placement algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-quality global routing for multiple dynamic supply voltage designs
Proceedings of the International Conference on Computer-Aided Design
Clustering-based simultaneous task and voltage scheduling for NoC systems
Proceedings of the International Conference on Computer-Aided Design
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI
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Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the voltage island technique has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are the two important steps in the design process. We propose a new application-driven, floorplan-aware approach to voltage partitioning and island creation with the objective of reducing overall SoC power, area and runtime. Previous approaches used the voltage assignment table as the starting point for voltage island creation. In this paper, we present a technique to generate a voltage assignment table using dynamic programming. Next, we partition the cores into islands, based on the Power State Model (PSM) of the application, and connectivity information used in floorplanning. Finally, solutions are sent to the floorplanner in sequence until a valid solution is reached. Compared to previously reported techniques, a 10% reduction in power and 8% reduction in area are achieved using our approach, with an average runtime improvement of 2.3X.