Temperature-Aware Voltage Islands Architecting in System-on-Chip Design

Authors:
W.-L. Hung;G. M. Link;Yuan Xie;N. Vijaykrishnan;N. Dhanwad;J. Conner
Affiliations:
Department of CSE, The Pennsylvania State University, University Park, PA;Department of CSE, The Pennsylvania State University, University Park, PA;Department of CSE, The Pennsylvania State University, University Park, PA;Department of CSE, The Pennsylvania State University, University Park, PA;IBM EDA Laboratory, Hopewell Junction, NY;Department of CSE, The Pennsylvania State University, University Park, PA
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC performance, power, and reliability. In view of this, we present a hybrid optimization approach which aims at temperature reduction and hot spot elimination. We demonstrate that considerable improvement in the thermal distribution of a design can be achieved through careful voltage island partitioning, voltage level assignment, and voltage island foorplanning. The experimental results on MCNC benchmarks show significant improvement on the thermal profiles. To the best of our knowledge, this is the first work to explore the thermal impacts of voltage islands.