Optimal orientations of cells in slicing floorplan designs
Information and Control
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
The planar package planner for system designers
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
On finding most optimal rectangular package plans
DAC '82 Proceedings of the 19th Design Automation Conference
Placement algorithms for arbitrarily shaped blocks
DAC '79 Proceedings of the 16th Design Automation Conference
Array optimization for VLSI synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An investigation into statistical properties of partitioning and floorplanning problems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient floorplan area optimization
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Integrated placement for mixed macro cell and standard cell designs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An analytical approach to floorplan design and optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A static partitioning and mapping algorithm for conservative parallel simulations
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Array mapping in behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Hybrid floorplanning based on partial clustering and module restructuring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EXPLORER: an interactive floorplanner for design space exploration
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Performance driven floorplanning for FPGA based designs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Cluster refinement for block placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
VLSI/PCB placement with obstacles based on sequence-pair
Proceedings of the 1997 international symposium on Physical design
How good are slicing floorplans?
Proceedings of the 1997 international symposium on Physical design
Device-level early floorplanning algorithms for RF circuits
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Arbitrary rectilinear block packing based on sequence pair
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with range constraint
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Post-placement residual-overlap removal with minimal movement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fast and accurate estimation of floorplans in logic/high-level synthesis
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
An enhanced perturbing algorithm for floorplan design using the O-tree representation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Floorplan area minimization using Lagrangian relaxation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Faster and more accurate wiring evaluation in interconnect-centric floorplanning
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Slicing floorplan design with boundary-constrained modules
Proceedings of the 2001 international symposium on Physical design
ECBL: an extended corner block list with solution space including optimum placement
Proceedings of the 2001 international symposium on Physical design
Slicing floorplan with clustering constraints
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
VLSI floorplanning with boundary constraints based on corner block list
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Module placement with boundary constraints using the sequence-pair representation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
VLSI block placement using less flexibility first principles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Twin binary sequences: a non-redundant representation for general non-slicing floorplan
Proceedings of the 2002 international symposium on Physical design
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Modeling non-slicing floorplans with binary trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Genetic Approach for Two Dimensional Packing with Constraints
ICCS '01 Proceedings of the International Conference on Computational Science-Part II
Rectilinear block placement using B*-trees
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An optimum placement search algorithm based on extended corner block list
Journal of Computer Science and Technology
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
The effect of pin constraints on layout area
EDTC '95 Proceedings of the 1995 European conference on Design and Test
VLSI floorplan generation and area optimization using AND-OR graph search
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Macro Block Based FPGA Floorplanning
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Net Clustering Based Macrocell Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
An Upper Bound for 3D Slicing Floorplans
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Fast Hierarchical Floorplanning with Congestion and Timing Control
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Rectilinear Block Placement Using B*-Trees
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Constrained two dimensional bin packing using a genetic algorithm
Recent advances in intelligent paradigms and applications
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region
EURO-DAC '90 Proceedings of the conference on European design automation
A VLSI floorplanner based on "balloon" expansion
EURO-DAC '90 Proceedings of the conference on European design automation
Datapath optimization using feedback
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Effective Congestion Model in Floorplan Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement
Journal of VLSI Signal Processing Systems
Deterministic VLSI block placement algorithm using less flexibility first principle
Journal of Computer Science and Technology
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Practical slicing and non-slicing block-packing without simulated annealing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Stairway compaction using corner block list and its applications with rectilinear blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Annealing placement by thermodynamic combinatorial optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Abstraction and optimization of consistent floorplanning with pillar block constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Space-planning: placement of modules with controlled empty area by single-sequence
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On handling arbitrary rectilinear shape constraint
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Robust fixed-outline floorplanning through evolutionary search
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Floorplan design for multi-million gate FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Non-slicing floorplans with boundary constraints using generalized polish expression
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Floorplanning with power supply noise avoidance
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
CMP aware shuttle mask floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
LFF algorithm for heterogeneous FPGA floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wirelength optimization by optimal block orientation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Integrated Computer-Aided Engineering
Fixed-outline floorplanning using robust evolutionary search
Engineering Applications of Artificial Intelligence
Voltage- and ABB-island optimization in high level synthesis
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Power-density aware floorplanning for reducing maximum on-chip temperature
MOAS'07 Proceedings of the 18th conference on Proceedings of the 18th IASTED International Conference: modelling and simulation
Voltage island-driven floorplanning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Data mining with a simulated annealing based fuzzy classification system
Pattern Recognition
Data mining with a simulated annealing based fuzzy classification system
Pattern Recognition
Variable-sized object packing and its applications to instruction cache design
Computers and Electrical Engineering
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Supply chain risks analysis by using jump-diffusion model
Proceedings of the 40th Conference on Winter Simulation
Solving facility layout problems using genetic programming
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
A Parallel Simulated Annealing Approach for Floorplanning in VLSI
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Power-density aware floorplanning for reducing maximum on-chip temperature
MS '07 The 18th IASTED International Conference on Modelling and Simulation
An efficient macro-cell placement algorithm
Integration, the VLSI Journal
How good are slicing floorplans?
Integration, the VLSI Journal
Hybrid algorithm for floorplanning using B*-tree representation
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
Multi-objective floorplanning based on fuzzy logic
FSKD'09 Proceedings of the 6th international conference on Fuzzy systems and knowledge discovery - Volume 4
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Configurable multi-product floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Floorplanning for low power IC design considering temperature variations
Microelectronics Journal
Parallel cross-layer optimization of high-level synthesis and physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fuzzy model tuning using simulated annealing
Expert Systems with Applications: An International Journal
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplanning with IR-drop consideration
ICOSSSE'05 Proceedings of the 4th WSEAS/IASME international conference on System science and simulation in engineering
Floorplanning algorithm for multiple clock domains
ICOSSSE'05 Proceedings of the 4th WSEAS/IASME international conference on System science and simulation in engineering
Hotspots elimination and temperature flattening in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A theoretical upper bound for IP-based floorplanning
COCOON'05 Proceedings of the 11th annual international conference on Computing and Combinatorics
Transformation from ad hoc EDA to algorithmic EDA
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
On improved least flexibility first heuristics superior for packing and stock cutting problems
SAGA'05 Proceedings of the Third international conference on StochasticAlgorithms: foundations and applications
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Practically scalable floorplanning with voltage island generation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Performance-driven analog placement considering monotonic current paths
Proceedings of the International Conference on Computer-Aided Design
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Area optimization on fixed analog floorplans using convex area functions
Proceedings of the Conference on Design, Automation and Test in Europe
Fast fixed-outline 3-D IC floorplanning with TSV co-placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constraint-aware interior layout exploration for pre-cast concrete-based buildings
The Visual Computer: International Journal of Computer Graphics
Journal of Integrated Design & Process Science
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We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.