Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Net partitions yield better module partitions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Anatomy of a Silicon Compiler
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Net-based force-directed macrocell placement for wirelength optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a net clustering based RT-level macro-cell placement approaches. Static timing analysis identifies critical nets and critical primary input/output paths. Net clustering (based on shared macro-cells and net criticality) yields clusters wherein each cluster has strongly interdependent nets. The circuit is modeled as a graph in which each vertex v represents a net and each edge (v,u) a shared cell between nets v and u. The net clusters are obtained by applying a clique partitioning algorithm on the circuit graph. Two approaches to generate placements at RTL are proposed: constructive (cluster growth) approach and iterative improvement (simulated annealing) based approach. In the constructive approach, a cluster-level floorplanning is performed and a cluster ordering is obtained. The cluster ordering is used by a constructive procedure to generate the physical placement. In the case of iterative improvement based approach, a good ordering of clusters is obtained using simulated annealing.We report experimental results for five RTL datapaths implemented in 0.35 μm technology to demonstrate the efficacy of the proposed approaches. We compared the layouts produced by our approaches with those produced by Flint, an automatic floor planner in Lager IV Silicon Compiler [1]. For constructive placement approach, we obtained an average decrease of 43.4% in longest wirelength and 32.4% in total wirelength. The average area reduction is 7.3%. On the other hand, for the SA-based approach, we obtained an average decrease of 57.6% in longest wirelength and 42.2% in total wirelength. The average reduction in the bounding-box area is 12.3%. As expected, the SA-based approach yielded better optimization results, due to its ability to climb out of local minima.