Worst-case growth rates of some classical problems of combinatorial optimization
SIAM Journal on Computing
A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A Priori Bounds on the Euclidean Traveling Salesman
SIAM Journal on Computing
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Improved Steiner tree approximation in graphs
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
Toward better wireload models in the presence of obstacles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
RPack: routability-driven packing for cluster-based FPGAs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Toward better wireload models in the presence of obstacles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement
Journal of VLSI Signal Processing Systems
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
On the partial terminal Steiner tree problem
The Journal of Supercomputing
A near linear time approximation scheme for Steiner tree among obstacles in the plane
Computational Geometry: Theory and Applications
On the full and bottleneck full Steiner tree problems
COCOON'03 Proceedings of the 9th annual international conference on Computing and combinatorics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An improved approximation algorithm for the terminal Steiner tree problem
ICCSA'11 Proceedings of the 2011 international conference on Computational science and its applications - Volume Part III
Algorithms on graphs with small dominating targets
ISAAC'06 Proceedings of the 17th international conference on Algorithms and Computation
The internal Steiner tree problem: Hardness and approximations
Journal of Complexity
| Hi-index | 0.00 |
Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop new wirelength estimation techniques appropriate for top-down floor-planning and placement synthesis of row-based VLSI layouts. Our methods include accurate, linear-time approaches, often with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). The new techniques offer advantages not only for early on-line wirelength estimation during top-down placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several theoretical contributions. Notably, we have resolved the long-standing discrepancy between region-based and bounding box-based RSMT estimation techniques; this leads to new estimates that are functions of instance size n and aspect ratio AR.