Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Battery-Driven System Design: A New Frontier in Low Power Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power Aware Interface Synthesis for Bus-Based SoC Designs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
High-level power analysis for on-chip networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Compiler-directed proactive power management for networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Proceedings of the 2006 international workshop on System-level interconnect prediction
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Communication latency aware low power NoC synthesis
Proceedings of the 43rd annual Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Application-Specific Design Methodology for On-Chip Crossbar Generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of optimized hardware transactors from abstract communication specifications
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Embedded RAIDs-on-chip for bus-based chip-multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
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On-chip communication architectures have a significant impact on the power consumption and performance of emerging chip multiprocessor (CMP) applications. However, customization of such architectures for an application requires the exploration of a large design space. Designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper, we present an automated framework for fast system-level, application-specific, power-performance tradeoffs in a bus matrix communication architecture synthesis (CAPPS). Our study makes two specific contributions. First, we develop energy models for system-level exploration of bus matrix communication architectures. Second, we incorporate these models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macromodels incur less than 5% average cycle energy error across 180-65 nm technology libraries. Our early system-level power estimation approach also shows a significant speedup ranging from 1000 to 2000× when compared with detailed gate-level power estimation. Furthermore, on applying our synthesis framework to three industrial networking CMP applications, a tradeoff space that exhibits up to 20% variation in power and up to 40% variation in performance is generated, demonstrating the usefulness of our approach.