Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Arbitrary convex and concave rectilinear block packing using sequence-pair
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Post-placement residual-overlap removal with minimal movement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An enhanced perturbing algorithm for floorplan design using the O-tree representation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Floorplan area minimization using Lagrangian relaxation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
Floorplan sizing by linear programming approximation
Proceedings of the 37th Annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
A fast algorithm for context-aware buffer insertion
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Constrained "Modern" Floorplanning
Proceedings of the 2003 international symposium on Physical design
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Silicon virtual prototyping: the new cockpit for nanometer chip design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design flow and methodology for 50M gate ASIC
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Practical slicing and non-slicing block-packing without simulated annealing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Improved Multi-Level Framework for Force-Directed Placement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Processing Rate Optimization by Sequential System Floorplanning
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
How does partitioning matter for 3D floorplanning?
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Wirelength optimization by optimal block orientation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Constraint-driven floorplan repair
Proceedings of the 43rd annual Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout aware design of mesh based NoC architectures
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A stable fixed-outline floorplanning method
Proceedings of the 2007 international symposium on Physical design
Fast wire length estimation by net bundling for block placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Microarchitecture floorplanning for sub-threshold leakage reduction
Proceedings of the conference on Design, automation and test in Europe
Fixed-outline floorplanning using robust evolutionary search
Engineering Applications of Artificial Intelligence
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Elastic Flow in an Application Specific Network-on-Chip
Electronic Notes in Theoretical Computer Science (ENTCS)
Large-scale fixed-outline floorplanning design using convex optimization techniques
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Interconnect modeling for improved system-level design optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
Constraint-driven floorplan repair
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Solving modern mixed-size placement instances
Integration, the VLSI Journal
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Linear constraint graph for floorplan optimization with soft blocks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Exploring adjacency in floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for constraint-driven synthesis of on-chip communications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Post-placement temperature reduction techniques
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
Physically-aware exploitation of component reuse in a partially reconfigurable architecture
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fixed-outline thermal-aware 3D floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Topology synthesis for low power cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning for low power IC design considering temperature variations
Microelectronics Journal
Evaluating carbon nanotube global interconnects for chip multiprocessor applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
E-beam lithography stencil planning and optimization with overlapped characters
Proceedings of the 2011 international symposium on Physical design
Design of network-on-chip architectures with a genetic algorithm-based technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffer planning for IP placement using sliced-LFF
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Floorplacement for partial reconfigurable FPGA-based systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Fast substrate noise aware floorplanning for mixed signal SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal signature: a simple yet accurate thermal index for floorplan optimization
Proceedings of the 48th Design Automation Conference
Thermal-aware floorplan schemes for reliable 3D multi-core processors
ICCSA'11 Proceedings of the 2011 international conference on Computational science and its applications - Volume Part II
Power profiling-guided floorplanner for thermal optimization in 3D multiprocessor architectures
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
System interconnect design exploration for embedded MPSoCs
Proceedings of the System Level Interconnect Prediction Workshop
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Temperature-aware floorplanning via geometric programming
Mathematical and Computer Modelling: An International Journal
Practically scalable floorplanning with voltage island generation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
Physical-aware system-level design for tiled hierarchical chip multiprocessors
Proceedings of the 2013 ACM international symposium on International symposium on physical design
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Variable-Order Ant System for VLSI multiobjective floorplanning
Applied Soft Computing
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Systems Architecture: the EUROMICRO Journal
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context.Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported [28]. A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.