Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing communication overlap for high-speed networks
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Communication Architecture Synthesis of Cascaded Bus Matrix
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Application-Specific Design Methodology for On-Chip Crossbar Generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Crossbar switch network has an increasing impact on such critical measures as throughput, latency, area, and power consumption of complex system-on-chip as technology scales to deep submicrometer. With high clock frequency crossbar switch network design, global wire delay and pipeline registers inserted for throughput are important because they affect area, frequency, and power consumption of the chip. The traffic congestion is also a very important factor because it leads to the lowering of throughput of the crossbar switch network. In this paper, we present a topology synthesis method for the low-power cascaded crossbar switch network satisfying the given bandwidth, latency, frequency, and area constraints. Unlike previous papers, our paper considers wire delay, traffic congestion, and pipeline register insertion at the same time. Experimental results show that the topologies optimized for power consumption for a given clock frequency consume less power than existing methods by up to 38.04%.