Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On-chip networks: A scalable, communication-centric embedded system design paradigm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
A Practical Approach for Bus Architecture Optimization at Transaction Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Fast Exploration of Bus-Based On-Chip Communication Architectures
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the conference on Design, automation and test in Europe
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Architecture exploration of NAND flash-based multimedia card
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design Trade-offs in Customized On-chip Crossbar Schedulers
Journal of Signal Processing Systems
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Interconnection synthesis of MPSoC architecture for gamma cameras
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Proceedings of the Conference on Design, Automation and Test in Europe
Topology synthesis for low power cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full bus matrix and up to 3.2 X savings when compared to a maximally connected reduced bus matrix.