Topology synthesis of cascaded crossbar switches

Authors:
Minje Jun;Sungjoo Yoo;Eui-Young Chung
Affiliations:
School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang, Korea;School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

Performance requirements of on-chip network increase as system-on-chips (SoCs) are becoming more and more complex. For high-performance applications, crossbar switch-based networks are replacing the traditional shared buses as the backbone networks in SoCs. In this paper, we tackle the topology design of on-chip networks with crossbar switches in a cascaded fashion. We also resolve the unacceptable complexity of our previous method based on mixed integer linear programming by a heuristic method. Experimental results show that the proposed method overcomes the frequency limitation of the single crossbar-based design, particularly when the wire delay effect is considered. The proposed heuristic method also achieves more area reduction (up to 69.5%) over the existing methods, and finds as good solutions as the exact method while the synthesis time is saved by orders of magnitude.