The rectilinear Steiner arborescence problem is NP-complete
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
Convex quadratic and semidefinite programming relaxations in scheduling
Journal of the ACM (JACM)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Early wire characterization for predictable network-on-chip global interconnects
Proceedings of the 2007 international workshop on System level interconnect prediction
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
IEEE Micro
Elastic Flow in an Application Specific Network-on-Chip
Electronic Notes in Theoretical Computer Science (ENTCS)
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Statistical Approach to NoC Design
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The era of many-modules SoC: revisiting the NoC mapping problem
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Circuits and Systems II: Express Briefs
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Proceedings of the Conference on Design, Automation and Test in Europe
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of low-overhead configurable source routing tables for network interfaces
Proceedings of the Conference on Design, Automation and Test in Europe
Application-specific 3D Network-on-Chip design using simulated allocation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A tree-based topology synthesis for on-chip network
Proceedings of the International Conference on Computer-Aided Design
System interconnect design exploration for embedded MPSoCs
Proceedings of the System Level Interconnect Prediction Workshop
Optimized 3D Network-on-Chip Design Using Simulated Allocation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A spectral clustering approach to application-specific network-on-chip synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-Specific Network-on-Chip synthesis with flexible router Placement
Journal of Systems Architecture: the EUROMICRO Journal
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Network-on-chip (NoC) has been proposed as a solution to the communication challenges of system-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. Custom NoC design in nanoscale technologies must address performance requirements, power consumption and physical layout considerations. This paper presents a novel three phase technique that i) generates a performance aware layout of the SoC, ii) maps the cores of the SoC to routers, and iii) generates a unique route for every trace that satisfies the performance and architectural constraints. We present an analysis of the quality of the results of the proposed technique by experimentation with realistic benchmarks.