Early wire characterization for predictable network-on-chip global interconnects

Authors:
Ilhan Hatirnaz;Stephane Badel;Nuria Pazos;Yusuf Leblebici;Srinivasan Murali;David Atienza;Giovanni De-Micheli
Affiliations:
LSM: EPFL, Lausanne, Switzerland;LSM: EPFL, Lausanne, Switzerland;LSM: EPFL, Lausanne, Switzerland;LSM: EPFL, Lausanne, Switzerland;CSL, Stanford, CA;LSM: EPFL, Lausanne, Switzerland;LSM: EPFL, Lausanne, Switzerland
Venue:
Proceedings of the 2007 international workshop on System level interconnect prediction
Year:
2007

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Abstract

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for upcoming nanometer technologies, where increased variations in both device characteristics and interconnect parameters introduce tedious design closure problems. The proposed methodology has been successfully applied to the wire synthesis of a Network-on-Chip interconnect to: (i) achieve a given delay and noise goals, and (ii) attain a more power-efficient design with respect to existing techniques.