“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 39th annual Design Automation Conference
Technology-based transformations
Logic Synthesis and Verification
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Bounding the efforts on congestion optimization for physical synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Design topology aware physical metrics for placement analysis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Hybrid hierarchical timing closure methodology for a high performance and low power DSP
Proceedings of the 40th annual Design Automation Conference
Layout-driven Timing Optimization by Generalized De Morgan Transform
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient timing closure without timing driven placement and routing
Proceedings of the 41st annual Design Automation Conference
Early wire characterization for predictable network-on-chip global interconnects
Proceedings of the 2007 international workshop on System level interconnect prediction
Efficient post-layout power-delay curve generation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Hi-index | 0.00 |
This paper describes an approach for tight integration between a synthesis and a placement tool. The purpose of this integration is to improve timing convergence of advanced microprocessors. It is shown that this approach results in "legal" placements with, in general, lower delay, and design size. More significantly, the number of iterations to reach a timing closure is reduced drastically. The wire length estimates that are being used to traditionally drive the timing optimization in synthesis are inadequate. Instead, the integrated approach leads to enhanced results as well as faster timing convergence. The impact of various parameters in synthesis and placement on the final results is shown.