Design methodology of a 200MHz superscalar microprocessor: SH-4
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
Timing closure: the solution and its problems
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Importance of CAD tools and methodology in high speed CPU design: invited talk
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Hierarchical physical design methodology for multi-million gate chips
Proceedings of the 2001 international symposium on Physical design
Design hierarchy guided multilevel circuit partitioning
Proceedings of the 2002 international symposium on Physical design
Physical hierarchy generation with routing congestion control
Proceedings of the 2002 international symposium on Physical design
Timing closure based on physical hierarchy
Proceedings of the 2002 international symposium on Physical design
Delay budgeting for a timing-closure-driven design method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Addressing the timing closure problem by integrating logic optimization and placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Deep Submicron Design Techniques for the 500MHz IBM S/390 G5 Custom Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
A flexibility aware budgeting for hierarchical flow timing closure
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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A hybrid hierarchical timing closure methodology has been developed to combine strength of the subchip based hierarchical timing closure method and flat design based logic-physical combined optimization method for a 1.5 million gate, high performance and ultra-low power DSP which has been used in a number of wireless applications. The principle and the implementation details of the methodology are provided.