Getting to the bottom of deep submicron

Incremental capacitance extraction and its application to iterative timing-driven detailed routing

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Partitioning by iterative deletion

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Subwavelength optical lithography: challenges and impact on physical design

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Partitioning with terminals: a “new” problem and new benchmarks

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Getting to the bottom of deep submicron II: a global wiring paradigm

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Hypergraph partitioning with fixed vertices

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A novel VLSI layout fabric for deep sub-micron applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Subwavelength lithography and its potential impact on design and EDA

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Energy-efficient signal processing via algorithmic noise-tolerance

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Requirements for models of achievable routing

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Wiring layer assignments with consistent stage delays

SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction

GTX: the MARCO GSRC technology extrapolation system

Proceedings of the 37th Annual Design Automation Conference

A methodology for correct-by-construction latency insensitive design

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

What is the cost of delay insensitivity?

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Interconnect scaling implications for CAD

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Meeting delay constraints in DSM by minimal repeater insertion

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Optimization of error detecting codes for the detection of crosstalk originated errors

Proceedings of the conference on Design, automation and test in Europe

Overcoming wireload model uncertainty during physical design

Proceedings of the 2001 international symposium on Physical design

Post-layout transistor sizing for power reduction in cell-based design

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Design technology productivity in the DSM era (invited talk)

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

High-level synthesis under multi-cycle interconnect delay

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Achieving 550 MHz in an ASIC methodology

Proceedings of the 38th annual Design Automation Conference

Timing driven placement using physical net constraints

Proceedings of the 38th annual Design Automation Conference

System-level interconnect architecture exploration for custom memory organizations

Proceedings of the 14th international symposium on Systems synthesis

Understanding and addressing the impact of wiring congestion during technology mapping

Proceedings of the 2002 international symposium on Physical design

Global clustering-based performance-driven circuit partitioning

Proceedings of the 2002 international symposium on Physical design

Soft digital signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design

Power estimation in global interconnects and its reduction using a novel repeater optimization methodology

Proceedings of the 39th annual Design Automation Conference

Estimation of the likelihood of capacitive coupling noise

Proceedings of the 39th annual Design Automation Conference

Logical and physical design: a flow perspective

Logic Synthesis and Verification

The future of logic synthesis and verification

Logic Synthesis and Verification

From blind certainty to informed uncertainty

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Efficient switching window computation for cross-talk noise

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits

Analog Integrated Circuits and Signal Processing

Reconfigurable Computing for Digital Signal Processing: A Survey

Journal of VLSI Signal Processing Systems

Effects of global interconnect optimizations on performance estimation of deep submicron design

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Behavior-to-placed RTL synthesis with performance-driven placement

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

The scaling challenge: can correct-by-construction design help?

Proceedings of the 2003 international symposium on Physical design

Timing driven force directed placement with physical net constraints

Proceedings of the 2003 international symposium on Physical design

Routing methodology for minimizing 1nterconnect energy dissipation

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Throughput-driven IC communication fabric synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Estimation of signal arrival times in the presence of delay noise

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Force directed mongrel with physical net constraints

Proceedings of the 40th annual Design Automation Conference

Hybrid hierarchical timing closure methodology for a high performance and low power DSP

Proceedings of the 40th annual Design Automation Conference

Improved a priori terconnect predictions and technology extrapolation in the GTX system

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)

Design of Asynchronous Controllers with Delay Insensitive Interface

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

System-Level Point-to-Point Communication Synthesis Using Floorplanning Information

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Identification of Crosstalk Switch Failures in Domino CMOS Circuits

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Realistic Worst-Case Modeling by Performance Level Principal Component Analysis

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Noise Safety Design Methodologies

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI

Proceedings of the 2003 international symposium on Low power electronics and design

Will networks on chip close the productivity gap?

Networks on chip

Trends in SLI design and their effect on test

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Driver modeling and alignment for worst-case delay noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

A low power approach to system level pipelined interconnect design

Proceedings of the 2004 international workshop on System level interconnect prediction

Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work

Proceedings of the conference on Design, automation and test in Europe - Volume 1

An Interconnect Channel Design Methodology for High Performance Integrated Circuits

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement

Journal of VLSI Signal Processing Systems

Power macromodeling of global interconnects considering practical repeater insertion

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Distributed Diagnosis of Interconnections in SoC and MCM Designs

Journal of Electronic Testing: Theory and Applications

Practical repeater insertion for low power: what repeater library do we need?

Proceedings of the 41st annual Design Automation Conference

Timing closure through a globally synchronous, timing partitioned design methodology

Proceedings of the 41st annual Design Automation Conference

Vectorless Analysis of Supply Noise Induced Delay Variation

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Multi-objective mapping for mesh-based NoC architectures

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

Closing the power gap between ASIC and custom: an ASIC perspective

Proceedings of the 42nd annual Design Automation Conference

Floorplan-aware automated synthesis of bus-based communication architectures

Proceedings of the 42nd annual Design Automation Conference

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Proceedings of the 42nd annual Design Automation Conference

Power reduction techniques for microprocessor systems

ACM Computing Surveys (CSUR)

Impact of interconnect resistance increase on system performance of low power and high performance designs

Proceedings of the 2006 international workshop on System-level interconnect prediction

Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

An integrated performance and power model for superscalar processor designs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC

Proceedings of the conference on Design, automation and test in Europe: Proceedings

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

Proceedings of the 41st annual Design Automation Conference

A new hybrid FPGA with nanoscale clusters and CMOS routing

Proceedings of the 43rd annual Design Automation Conference

FABSYN: floorplan-aware bus architecture synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Microminiature packaging and integrated circuitry: the work of E. F. Rent, with an application to on-chip interconnection requirements

IBM Journal of Research and Development - POWER5 and packaging

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory

IEEE Transactions on Computers

Fast wire length estimation by net bundling for block placement

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

On optimal ordering of signals in parallel wire bundles

Integration, the VLSI Journal

Fast exploration of bus-based communication architectures at the CCATB abstraction

ACM Transactions on Embedded Computing Systems (TECS)

Low-power FinFET circuit synthesis using multiple supply and threshold voltages

ACM Journal on Emerging Technologies in Computing Systems (JETC)

Power-delay optimization in VLSI microprocessors by wire spacing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Handling routability in floorplan design with twin binary trees

Integration, the VLSI Journal

Scalability of network-on-chip communication architecture for 3-D meshes

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

Microelectronics Journal

Impact of local interconnects on timing and power in a high performance microprocessor

Proceedings of the 19th international symposium on Physical design

Low-power FinFET circuit synthesis using surface orientation optimization

Proceedings of the Conference on Design, Automation and Test in Europe

a fuzzy model for path delay fault detection

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Synchronous design flow for globally asynchronous locally synchronous systems

ICC'06 Proceedings of the 10th WSEAS international conference on Circuits

Crosstalk noise reduction in synthesized digital logic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A study on factors influencing power consumption in multithreaded and multicore CPUs

WSEAS Transactions on Computers

PASCOM: power model for supercomputers

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems

Co-optimization of performance and power in a superscalar processor design

EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing

Exploration of heuristic scheduling algorithms for 3D multicore processors

Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems

A greedy heuristic approximation scheduling algorithm for 3d multicore processors

Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing

Modeling symmetrical independent gate FinFET using predictive technology model

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Optimal placement of vertical connections in 3D Network-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal