Achieving 550 MHz in an ASIC methodology

Authors:
D. G. Chinnery;B. Nikolic;K. Keutzer
Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

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Abstract

Typically, good automated ASIC designs may be two to five times slower than handcrafted custom designs. At last year's DAC this was examined and causes of the speed gap between custom circuits and ASICs were identified. In particular, faster custom speeds are achieved by a combination of factors: good architecture with well-balanced pipelines; compact logic design; timing overhead minimization; careful floorplanning, partitioning and placement; dynamic logic; post-layout transistor and wire sizing; and speed binning of chips. Closing the speed gap requires improving these same factors in ASICs, as far as possible. In this paper we examine a practical example of how these factors may be improved in ASICs. In particular we show how techniques commonly found in custom design were applied to design a high-speed 550 MHz disk drive read channel in an ASIC design flow.