Fixed-phase retiming for low power design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
Efficient equivalence checking of multi-phase designs using retiming
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Achieving 550 MHz in an ASIC methodology
Proceedings of the 38th annual Design Automation Conference
A practical and efficient method for compare-point matching
Proceedings of the 39th annual Design Automation Conference
A Practical Algorithm for Retiming Level-Clocked Circuits
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Retiming of Circuits with Single Phase Transparent Latches
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Optimizing large multiphase level-clocked circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Latch circuits have advantage for timing and are widely used for high-speed custom circuits. However, ASIC design flows are based on the circuits with flip-flops. Then, ASIC designers don't use latches. This paper describes a new timing optimization algorithm for ASIC by replacing flip-flops to latches without changing the functionality of the circuits. After latch replacement, restricted retiming called fixed-phase retiming is carried out for timing optimization by minimizing the impact of clock skew and jitter. The experimental results show that 17% delay improvement of the benchmark circuits is achieved by proposed algorithms.