Fixed-phase retiming for low power design

Layout aware retiming

GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI

Optimization of synchronous circuits

Logic Synthesis and Verification

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Timing optimization by replacing flip-flops to latches

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

An approach for reducing dynamic power consumption in synchronous sequential digital designs

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization

Proceedings of the 2006 international symposium on Physical design

Flip-flop insertion with shifted-phase clocks for FPGA power reduction

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

A low-power content-adaptive texture mapping architecture for real-time 3D graphics

PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems

Simultaneous slack budgeting and retiming for synchronous circuits optimization

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

A statistical approach to the timing-yield optimization of pipeline circuits

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation