Retiming sequential circuits for low power

Precomputation-based sequential logic optimization for low power

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A methodology for efficient estimation of switching activity in sequential logic circuits

DAC '94 Proceedings of the 31st annual Design Automation Conference

A new power estimation technique with application to decomposition of Boolean functions for low power

EURO-DAC '94 Proceedings of the conference on European design automation

A survey of optimization techniques targeting low power VLSI circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Variable voltage scheduling

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

POSE: power optimization and synthesis environment

DAC '96 Proceedings of the 33rd annual Design Automation Conference

State assignment for FSM low power design

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Lower bounds on power dissipation for DSP algorithms

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Fixed-phase retiming for low power design

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

An improved algorithm for minimum-area retiming

DAC '97 Proceedings of the 34th annual Design Automation Conference

Power-conscious high level synthesis using loop folding

DAC '97 Proceedings of the 34th annual Design Automation Conference

High-level power modeling, estimation, and optimization

DAC '97 Proceedings of the 34th annual Design Automation Conference

Finite state machine decomposition for low power

DAC '98 Proceedings of the 35th annual Design Automation Conference

Low-Power Divider

IEEE Transactions on Computers

Glitch power minimization by gate freezing

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Performance driven resynthesis by exploiting retiming-induced state register equivalence

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Minimizing sensitivity to delay variations in high-performance synchronous circuits

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Maximizing performance by retiming and clock skew scheduling

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Retiming-based factorization for sequential logic optimization

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Layout aware retiming

GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI

Data driven power optimization of sequential circuits

Proceedings of the conference on Design, automation and test in Europe

Retiming-based logic synthesis for low-power

Proceedings of the 2002 international symposium on Low power electronics and design

Optimization of synchronous circuits

Logic Synthesis and Verification

HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space

HiPC '02 Proceedings of the 9th International Conference on High Performance Computing

An Efficient Random Number Generation Architecture for Hardware Parallel Genetic Algorithms

PPSN VI Proceedings of the 6th International Conference on Parallel Problem Solving from Nature

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Variables bounding based retiming algorithm

Journal of Computer Science and Technology

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT

Journal of VLSI Signal Processing Systems

Optimization of combinational and sequential logic circuits for low power using precomputation

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Retiming with Interconnect and Gate Delay

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

An approach for reducing dynamic power consumption in synchronous sequential digital designs

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

High Speed FPGA-Based Implementations of Delayed-LMS Filters

Journal of VLSI Signal Processing Systems

Bipartitioning and encoding in low-power pipelined circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization

Proceedings of the 2006 international symposium on Physical design

GlitchLess: an active glitch minimization technique for FPGAs

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Low Power VLSI Design Techniques - The Current State

Integrated Computer-Aided Engineering

Using negative edge triggered ffs to reduce glitching power in FPGA circuits

Proceedings of the 44th annual Design Automation Conference

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops

Proceedings of the 13th international symposium on Low power electronics and design

Scheduling with multiple voltages

Integration, the VLSI Journal

Retiming: Theory and practice

Integration, the VLSI Journal

Simultaneous slack budgeting and retiming for synchronous circuits optimization

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Re-synthesis for cost-efficient circuit-level timing speculation

Proceedings of the 48th Design Automation Conference

Relax-and-retime: a methodology for energy-efficient recovery based design

Proceedings of the 50th Annual Design Automation Conference