Minimizing sensitivity to delay variations in high-performance synchronous circuits

Clock Skew Optimization

IEEE Transactions on Computers

TIM: a timing package for two-phase, level-clocked circuitry

DAC '93 Proceedings of the 30th international Design Automation Conference

Resynthesis and retiming for optimum partial scan

DAC '94 Proceedings of the 31st annual Design Automation Conference

DELAY: an efficient tool for retiming with realistic delay modeling

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Optimal clock skew scheduling tolerant to process variations

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Optimizing two-phase, level-clocked circuitry

Journal of the ACM (JACM)

Retiming sequential circuits for low power

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Retiming of Circuits with Single Phase Transparent Latches

ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors

Incorporating interconnect, register, and clock distribution delays into the retiming process

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems