A new polynomial-time algorithm for linear programming
Combinatorica
Solving minimum-cost flow problems by successive approximation
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
Introduction to algorithms
IEEE Transactions on Computers
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
A zero-skew clock routing scheme for VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Retiming with non-zero clock skew, variable register, and interconnect delay
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ACM Computing Surveys (CSUR)
A fresh look at retiming via clock skew optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
Minimizing sensitivity to delay variations in high-performance synchronous circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Efficient retiming under a general delay model
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing large multiphase level-clocked circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming and clock scheduling for digital circuit optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Data dependency constraints constitute a lower bound P on the minimal clock period of single-phase clocked sequential circuits. In contrast to methods based on basic retiming, clocked sequential circuits with clock period P can always be obtained using software pipelining techniques. Such circuits can be derived by any method that can be framed in the following four-step process: Step 1, determine P; Step 2, compute a valid periodic schedule of the computational elements; Step 3, place registers back to the circuit; Step 4, assign the clock signals to control registers.Methods with polynomial run-time to implement this process are proposed in the literature. They implement these steps sequentially, starting with Step 1. These methods do not know how to optimally place registers which leads to an unnecessary number of registers. In this article, we address the problem of how to simultaneously implement Steps 2 and 3 in order to minimize the total number of registers. We conjecture that the problem is NP-hard in its general form. We formulate the problem for the first time in the literature, and devise a Mixed Integer Linear Program (MILP) to solve it. From this MILP, we derive a linear program to determine approximate solutions to the problem for large general circuits. We show that the proposed approach can handle nonzero clock skew. Experimental results confirm the effectiveness of the approach and show that significant reductions of the number of registers can be obtained although register sharing is not used. When the schedule is given, the proposed approach provides solutions to the problem of how to place the minimal number of registers in Step 3.