Theory of linear and integer programming
Theory of linear and integer programming
IEEE Transactions on Computers
Retiming with non-zero clock skew, variable register, and interconnect delay
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A timing analysis and optimization system for level-clocked circuitry
A timing analysis and optimization system for level-clocked circuitry
Understanding retiming through maximum average-delay cycles
Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming of Circuits with Single Phase Transparent Latches
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
| Hi-index | 0.00 |
The polynomial-time retiming algorithms that were developed in the eighties assumed simple delay models that neglected several timing issues that arise in logic design. Recent retiming algorithms for more comprehensive delay models rely on non-linear formulations and run in worst-case exponential time using branch-and-bound techniques. In this paper, we investigate the retiming problem for edge-triggered circuits under a general delay model that handles load-dependent gate delays, register delays, interconnect delays, and clock skew. We show that in this model the retiming problem can be expressed as a set of integer linear programming constraints that can be solved using general ILP techniques. For the special case where clock skew is monotonic and all registers have equal propagation delays, we give an integer phonotonic programming formulation of the retiming problem, and we present an efficient algorithm for solving it. Our algorithm retimes any given edge-triggered circuit to achieve a specified clock period in O(V/sup 3/F) steps, where V is the number of logic gales in the circuit and F is bounded by the number of registers in the circuit. A straightforward extension of our algorithm determines a minimum clock period retiming in O(V/sup 3/Flg V) steps.