The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
The PORT Mathematical Subroutine Library
ACM Transactions on Mathematical Software (TOMS)
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Placement for clock period minimization with multiple wave propagation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Retiming with non-zero clock skew, variable register, and interconnect delay
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Properties of Generalized Branch and Combine Clock Networks
IEEE Transactions on Parallel and Distributed Systems
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A fresh look at retiming via clock skew optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Useful-skew clock routing with gate sizing for low power design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Jitter-tolerant clock routing in two-phase synchronous systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Clocking Optimization and Distribution in Digital Systemswith Scheduled Skews
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
More practical bounded-skew clock routing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffer insertion for clock delay and skew minimization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Valid clocking in wavepipelined circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Minimizing sensitivity to delay variations in high-performance synchronous circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Maximizing performance by retiming and clock skew scheduling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A practical clock tree synthesis for semi-synchronous circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Marsh: min-area retiming with setup and hold constraints
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
The associative-skew clock routing problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clustering based fast clock scheduling for light clock-tree
Proceedings of the conference on Design, automation and test in Europe
Constrained clock shifting for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Optimization of synchronous circuits
Logic Synthesis and Verification
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound
IEEE Transactions on Parallel and Distributed Systems
Sequential delay budgeting with interconnect prediction
Proceedings of the 2003 international workshop on System-level interconnect prediction
Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip
Discrete Applied Mathematics
Delay budgeting in sequential circuit with application on FPGA placement
Proceedings of the 40th annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
On the performance of level-clocked circuits
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Efficient retiming under a general delay model
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Timing Correction and Optimization with Adaptive Delay Sequential Elements
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Clock Period Minimization of Non-Zero Clock Skew Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Skew-programmable clock design for FPGA and skew-aware placement
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
In-Circuit Self-Tuning of Clock Latencies
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Delay insertion method in clock skew scheduling
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Race-condition-aware clock skew scheduling
Proceedings of the 42nd annual Design Automation Conference
Yield-Driven, False-Path-Aware Clock Skew Scheduling
IEEE Design & Test
Digit-Recurrence Dividers with Reduced Logical Depth
IEEE Transactions on Computers
Temporal Decomposition for Logic Optimization
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast multi-domain clock skew scheduling for peak current reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Low area pipelined circuits by multi-clock cycle paths and clock scheduling
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Clock network minimization methodology based on incremental placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clock Skew Scheduling Under Process Variations
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Processing Rate Optimization by Sequential System Floorplanning
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Associative skew clock routing for difficult instances
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient incremental clock latency scheduling for large circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Register binding for clock period minimization
Proceedings of the 43rd annual Design Automation Conference
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
Proceedings of the 43rd annual Design Automation Conference
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Skew spreading for peak current reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Physical aware clock skew rescheduling
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A fast clock scheduling for peak power reduction in LSI
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
Self-tuning adaptive delay sequential elements
Microelectronics Journal
Clock skew scheduling with race conditions considered
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of rotary clock based circuits
Proceedings of the 44th annual Design Automation Conference
Effects of coupling capacitance and inductance on delay uncertainty and clock skew
Proceedings of the 44th annual Design Automation Conference
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A self-adjusting clock tree architecture to cope with temperature variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Early planning for clock skew scheduling during register binding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for sizing sequential circuits for industrial library based designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A fast incremental clock skew scheduling algorithm for slack optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Proceedings of the 45th annual Design Automation Conference
Skew-aware polarity assignment in clock tree
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing driven power gating in high-level synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Process variation mitigation via post silicon clock tuning
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Proceedings of the 46th Annual Design Automation Conference
Design of voltage overscaled low-power trellis decoders in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum-period register binding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Integration, the VLSI Journal
Accurate clock mesh sizing via sequential quadraticprogramming
Proceedings of the 19th international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast heuristic algorithm for multidomain clock skew scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock skew scheduling for soft-error-tolerant sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting clock skew scheduling for FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A practical method for multi-domain clock skew optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal multi-domain clock skew scheduling
Proceedings of the 48th Design Automation Conference
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers
Proceedings of the International Conference on Computer-Aided Design
Online clock skew tuning for timing speculation
Proceedings of the International Conference on Computer-Aided Design
Useful-skew clock optimization for multi-power mode designs
Proceedings of the International Conference on Computer-Aided Design
Simultaneous clock and data gate sizing algorithm with common global objective
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Co-synthesis of data paths and clock control paths for minimum-period clock gating
Proceedings of the Conference on Design, Automation and Test in Europe
Clock skew scheduling for timing speculation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
SmipRef: An efficient method for multi-domain clock skew scheduling
Integration, the VLSI Journal
Clock tree resynthesis for multi-corner multi-mode timing closure
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 14.99 |
Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.