IEEE Transactions on Computers
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Incorporating interconnect, register, and clock distribution delays into the retiming process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming and clock scheduling for digital circuit optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Race-condition-aware clock skew scheduling
Proceedings of the 42nd annual Design Automation Conference
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Clock skew scheduling with race conditions considered
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Co-synthesis of data paths and clock control paths for minimum-period clock gating
Proceedings of the Conference on Design, Automation and Test in Europe
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It is known that the clock skew can be exploited as a manageableresource to improve the circuit performance. However, due to thelimitation of race condition, the optimal clock skew schedulingdoes not achieve the lower bound of the clock period. In thispaper, we propose a polynomial time complexity algorithm, whichincorporates optimal clock skew scheduling and delay insertion,for the synthesis of non-zero clock skew circuits. The mainadvantages of our algorithm include two parts. First, it guaranteesto achieve the lower bound of the clock period. Secondly, it alsotries to minimize the required inserted delays under the lowerbound of the clock period. Experimental data shows that, eventhough we only use the buffers in a standard cell library toimplement the delay insertion, our approach still works well.