Clock Period Minimization of Non-Zero Clock Skew Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Digit-Recurrence Dividers with Reduced Logical Depth
IEEE Transactions on Computers
Clock skew scheduling with race conditions considered
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Minimum-period register binding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimization problems are explored: (1) clock period minimization and (2) tolerance maximization to clock-signal delay variations. Exact mixed-integer linear programming formulations and efficient heuristics are given for both problems. When both long and short paths are considered, circuits optimized by the combined application of retiming and clock scheduling can achieve shorter clock periods or demonstrate greater tolerance to clock-signal delay variations than circuits optimized by retiming or clock scheduling. Experiments with benchmark circuits demonstrate the effectiveness of the combined optimization. In comparison with the best result obtained by either of the two optimizations, the joint application of retiming and clock scheduling increased operating speeds by more than 8% on the average. It also increased tolerance to clock delay variations by an average of 12% over a broad range of target clock frequencies. Larger relative improvements were achieved for shorter clock periods, thus suggesting that simultaneous retiming and clock scheduling can play an important role in high-speed design