IEEE Transactions on Computers
Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Practical Fast Clock-Schedule Design Algorithms*The preliminary version was presented at [1].
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Retiming and clock scheduling for digital circuit optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay insertion method in clock skew scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.