Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A unified online fault detection scheme via checking of stability violation
Proceedings of the Conference on Design, Automation and Test in Europe
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
Co-synthesis of data paths and clock control paths for minimum-period clock gating
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. It is shown that reconvergent paths limit the improvement of circuit performance achievable through clock skew scheduling. A delay insertion method is proposed such that the optimal clock period achievable through clock skew scheduling is improved by mitigating the limitations caused by reconvergent paths. Experimental results demonstrate that reconvergent paths are limiting for 34% (41% for level sensitive) of the selected suite of ISCAS'89 benchmark circuits. Through the application of clock skew scheduling with delay insertion, an average improvement of 10% shorter clock periods (9% for level sensitive) is observed for ISCAS'89 benchmark circuits compared to the results of conventional clock skew scheduling.