Sensing circuit for on-line detection of delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Buffer Assignment Algorithms on Data Driven ASICs
IEEE Transactions on Computers
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
Design and CAD challenges in 45nm CMOS and beyond
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior
Proceedings of the 2009 International Conference on Computer-Aided Design
Delay insertion method in clock skew scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire Retiming Problem With Net Topology Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Online clock skew tuning for timing speculation
Proceedings of the International Conference on Computer-Aided Design
On logic synthesis for timing speculation
Proceedings of the International Conference on Computer-Aided Design
PushPull: short path padding for timing error resilient circuits
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Relax-and-retime: a methodology for energy-efficient recovery based design
Proceedings of the 50th Annual Design Automation Conference
Clock skew scheduling for timing speculation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ForTER: a forward error correction scheme for timing error resilience
Proceedings of the International Conference on Computer-Aided Design
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As the transistor feature size is continuously scaled down, integrated circuits are more vulnerable to process, voltage and temperature (PVT) variations, causing infrequent timing errors. Various techniques have been proposed to tackle this problem and circuit-level timing speculation is one of the most promising solutions. However, directly applying such technique can be quite costly in terms of area overhead and energy consumption. In this paper, we propose cost-efficient re-synthesis solutions to tackle this problem. We try to reduce the number of suspicious flip-flops (FFs) that might have timing errors by retiming techniques, which relocate some suspicious FFs without increasing critical path delay. An efficient and effective algorithm is then utilized to pad those short paths linking the remaining suspicious FFs to ensure the functional correctness of timing speculators. Experimental results show that the proposed solution can achieve significant area reduction for timing speculation.