Mapping data flow programs on a VLSI array of processors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
VLSI array processors
Computer algorithms: introduction to design and analysis
Computer algorithms: introduction to design and analysis
Integer and combinatorial optimization
Integer and combinatorial optimization
A Decomposition Approach for Balancing Large-Scale Acyclic Data Flow Graphs
IEEE Transactions on Computers
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
A Polynomial Algorithm for Balancing Acyclic Data Flow Graphs
IEEE Transactions on Computers
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Buffer assignment for data driven architectures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A data-driven multiprocessor architecture for high throughput digital signal processing
A data-driven multiprocessor architecture for high throughput digital signal processing
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
A general method for solving divide-and-conquer recurrences
ACM SIGACT News
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
| Hi-index | 14.98 |
Data driven architectures have significant potential in the design of high performance ASICs. By exploiting the inherent parallelism in the application, these architectures can maximize pipelining. The key consideration involved with the design of a data driven ASIC is ensuring that throughput is maximized while a relatively low area is maintained. Optimal throughput can be realized by ensuring that all operands arrive simultaneously at their corresponding operator node. If this condition is achieved, the underlying data flow graph is said to be balanced. If the initial data flow graph is unbalanced, buffers must be inserted to prevent the clogging of the pipeline along the shorter paths. A novel algorithm for the assignment of buffers in a data flow graph is proposed. The method can also be applied to achieve wave-pipelining in digital systems under certain restrictions. The algorithm uses a new application of the retiming technique; the number of buffers here is shown to be equal to the minimum number of buffers achieved by integer programming techniques. We also discuss an extension of this algorithm which can further reduce the number of buffers by altering the DFG without affecting functionality or performance. The time complexities of the proposed algorithms are O($V \times E$) and O($V^2 \times$logV), respectively, a considerable improvement over the existing strategies. Also proposed is a novel buffer distribution algorithm that exploits a unique feature of data driven operation. This procedure maximizes throughput by inserting substantially fewer buffers than other techniques. Experimental results show that the proposed algorithms outperform the existing methods.