Synthesis of optimal clocking schemes
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The ADAM advanced design automation system: overview, planner and natural language interface
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Synthesis of Hardware for the Control of Digital Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
LASSIE: structure to layout for behavioral synthesis tools
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A technology-adaptive allocation of functional units and connections
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VHDL synthesis using structured modeling
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Representing conditional branches for high-level synthesis applications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Constraint sensitive scheduling in RASP
ACM SIGDA Newsletter
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A generalized interconnect model for data path synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Global hardware synthesis from behavioral dataflow descriptions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A global, dynamic register allocation and binding for a data path synthesis system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fast and near optimal scheduling in automatic data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Empirical evaluation of some high-level synthesis scheduling heuristics
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Superpipelined control and data path synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
A neural network based algorithm for the scheduling problem in high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Estimating architectural resources and performance for high-level synthesis applications
DAC '93 Proceedings of the 30th international Design Automation Conference
A tree-based scheduling algorithm for control-dominated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
Scheduling of behavioral VHDL by retiming techniques
EURO-DAC '94 Proceedings of the conference on European design automation
High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
IEEE Transactions on Parallel and Distributed Systems
An optimal clock period selection method based on slack minimization criteria
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock optimization for high-performance pipelined design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
SMASH: a program for scheduling memory-intensive application-specific hardware
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Code generation for a DSP processor
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
How datapath allocation affects controller delay
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Limited exception modeling and its use in presynthesis optimizations
DAC '97 Proceedings of the 34th annual Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Transforming control-flow intensive designs to facilitate power management
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register Allocation—A Hierarchical Reduction Approach
Journal of VLSI Signal Processing Systems
Timing analysis in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A partitioning algorithm for system-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Buffer Assignment Algorithms on Data Driven ASICs
IEEE Transactions on Computers
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A symbolic approach for the combined solution of scheduling and allocation
Proceedings of the 15th international symposium on System Synthesis
From Behavior to Structure: High-Level Synthesis
IEEE Design & Test
An Optimizer for Hardware Synthesis
IEEE Design & Test
IEEE Design & Test
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Lower bound estimation of hardware resources for scheduling in high-level synthesis
Journal of Computer Science and Technology
Symbolic Binding for Clustered VLIW ASIPs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
EURO-DAC '90 Proceedings of the conference on European design automation
A neural net based self organising scheduling algorithm
EURO-DAC '90 Proceedings of the conference on European design automation
A design representation for high level synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Achieving Design Closure Through Delay Relaxation Parameter
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Journal of VLSI Signal Processing Systems
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
A low-power scheduling tool for system on a chip designs
WSEAS Transactions on Circuits and Systems
Optimal synthesis of control logic from behavioral specifications
Integration, the VLSI Journal
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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MAHA is a program which implements an algorithm for register level synthesis of data paths from a data flow specification. The algorithm is based on a linear hardware assignment to critical path nodes, followed by a cost-based assignment using the concept of the freedom of a node to be scheduled. Functions with the least scheduling freedom are scheduled first. The program either minimizes cost, subject to a time constraint, or maximizes speed subject to a cost constraint. The implementation of this algorithm is presented using examples from the literature.MAHA is written in Franz LISP, and executes within minutes for problems of practical size on a VAX 11/780.