Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Empirical evaluation of some high-level synthesis scheduling heuristics
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automata-based symbolic scheduling
Automata-based symbolic scheduling
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast timing closure by interconnect criticality driven delay relaxation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Wavesched: a novel scheduling technique for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating speculative execution into scheduling of control-flow-intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior and communication co-optimization for systems with sequential communication media
Proceedings of the 43rd annual Design Automation Conference
Pattern-based behavior synthesis for FPGA resource reduction
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scheduling with integer time budgeting for low-power optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A variation-tolerant scheduler for better than worst-case behavioral synthesis
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Scheduling with soft constraints
Proceedings of the 2009 International Conference on Computer-Aided Design
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Variation-aware layout-driven scheduling for performance yield optimization
Proceedings of the International Conference on Computer-Aided Design
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Efficient design space exploration for component-based system design
Proceedings of the International Conference on Computer-Aided Design
Multi-pumping for resource reduction in FPGA high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
Combining computation and communication optimizations in system synthesis for streaming applications
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Fast and effective placement and routing directed high-level synthesis for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
From software to accelerators with LegUp high-level synthesis
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
SDC-based modulo scheduling for pipeline synthesis
Proceedings of the International Conference on Computer-Aided Design
From design to design automation
Proceedings of the 2014 on International symposium on physical design
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Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most of the existing behavior-level scheduling heuristics either have a limited efficiency in a specific class of applications or lack general support of various design constraints.In this paper we describe a new scheduler that converts a rich set of scheduling constraints into a system of difference constraints (SDC) and performs a variety of powerful optimizations under a unified mathematical programming framework. In particular, we show that our SDC-based scheduling algorithm can efficiently support resource constraints, frequency constraints, latency constraints, and relative timing constraints, and effectively optimize longest path latency, expected overall latency, and the slack distribution. Experiments demonstrate that our proposed technique provides efficient solutions for a broader range of applications with higher quality of results (in terms of system performance) when compared to the state-of-the-art scheduling heuristics.