Empirical evaluation of some high-level synthesis scheduling heuristics
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Protocol generation for communication channels
DAC '94 Proceedings of the 31st annual Design Automation Conference
The Chinook hardware/software co-synthesis system
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Interface co-synthesis techniques for embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Integrating communication protocol selection with partitioning in hardware/software codesign
Proceedings of the 11th international symposium on System synthesis
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
A Loop Transformation Theory and an Algorithm to Maximize Parallelism
IEEE Transactions on Parallel and Distributed Systems
Interface Synthesis using Memory Mapping for an FPGA Platform
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
Interface synthesis in heterogeneous system-level DSP design tools
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 02
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Formal Verification for High-Assurance Behavioral Synthesis
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Equivalence checking for behaviorally synthesized pipelines
Proceedings of the 49th Annual Design Automation Conference
Improving high level synthesis optimization opportunity through polyhedral transformations
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writing sequence must have the same order, different transmission orders may have a dramatic impact on the final performance. However, the problem of determining the best possible communication order for SCMs is not adequately addressed by prior work. The goal of our work is to consider behaviors in communication synthesis for SCM, detect appropriate transmission order to optimize latency, automatically transform the behavior descriptions, and automatically generate driver routines and glue logics to access physical channels. Our algorithm, named SCOOP, successfully achieves these goals by behavior and communication co-optimization. Compared to the results without optimization, we can achieve an average 20% improvement in total latency on a set of real-life benchmarks.