Behavior and communication co-optimization for systems with sequential communication media
Proceedings of the 43rd annual Design Automation Conference
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Several system-on-chip (SoC) platforms have recently emerged thatuse reconfigurable logic (FPGAs) as a programmable co-processor toreduce the computational load on the main processor core. In thispaper, we present an interface synthesis approach that forms partof our hardware-software co-design methodology for such anFPGA-based platform. The approach is based on a novel memorymapping algorithm that maps data used by both the hardware and thesoftware to shared memories on the reconfigurable fabric. Thememory mapping algorithm couples with a high-level synthesis tooland uses scheduling information to map variables, arrays andcomplex data structures to the shared memories in a way thatminimizes the number of registers and multiplexers used in thehardware interface. We also present three software schemes thatenable the application software to communicate with this hardwareinterface. We demonstrate the utility of our approach and study thetrade-offs involved using a case study of the co-design of acomputationally expensive portion of the MPEG-1 multimediaapplication on to the Altera Nios platform.