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Theoretical Computer Science
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DIPES '00 Proceedings of the IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems: Architecture and Design of Distributed Embedded Systems
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Electronic Notes in Theoretical Computer Science (ENTCS)
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing equivalence checking for behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Equivalence checking for behaviorally synthesized pipelines
Proceedings of the 49th Annual Design Automation Conference
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Proceedings of the 50th Annual Design Automation Conference
Microprocessors & Microsystems
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We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We show how to decompose this certification into two components, which can be respectively handled by the complementary verification techniques, theorem proving and model checking. The approach produces a certified reference flow, composed of transformations distilled from production synthesis tools but represented as transformations on graphs with an associated formal semantics. This tool-independent abstraction disentangles our framework from the inner workings of specific synthesis tools while permitting certification of hardware designs generated from a broad class of behavioral descriptions. We provide experimental results suggesting the scalability on practical designs.